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| IRPP3624-05A POWIR+ Chipset Reference Design #0611 5Amp Single Phase Synchronous Buck POWIR+TM Chipset Reference Design using IR3624MPBF PWM & Driver IC and IRF9910PBF Dual SO-8 MOSFET By Steve Oknaian, Senior Applications Engineer www.irf.com RD#0611 1 Table of Contents Page Introduction ..........................................................................................3 Design Details ......................................................................................3 Start-Up Procedure ..............................................................................4 Layout Considerations .........................................................................4 Circuit Schematic .................................................................................6 Complete Bill of Materials.....................................................................7 PCB layouts .........................................................................................8-9 Electrical Efficiency & Power Loss .......................................................10 Thermal Performance & Bode Plot.......................................................11 Input & Output Ripple Waveforms........................................................12 Load Step Waveforms..........................................................................13 Power Up & Power Down Waveforms..................................................14 IRPP3637-xxA Reference Design Selector Table ................................15 www.irf.com RD#0611 2 Introduction The IRPP3624-05A is an optimized POWIR+TM Chipset reference design, targeted at low cost, low power synchronous buck applications up to 5A output current. The IRPP3624-05A uses International Rectifier's IR3624MPBF single channel, 600kHz fixed switching frequency PWM controller in a 10-pin MLPD and IRF9910PBF dual SO-8 MOSFET. This reference design has built-in power design expertise regarding component selection and PCB layout, and is representative of a realistic final embedded synchronous buck design, intended to simplify the design in effort without unnecessary design iterations. The design is optimized for 12V input and 3.3V output @ 5A, including considerations on layout and passive & magnetic component selection. The IRPP362405A delivers the complete 5A design in less than 0.5in2 board area at up to 88% full load electrical efficiency. International Rectifier also offers the POWIR+ Chipset on-line design tool (http://powirplus.irf.com) allowing the customization of the IRPP3624-05A reference design to meet individual requirements. Based on specific inputs, the POWIR+ Chipset on-line design tool will provide a tailored schematic and bill of materials, from which the engineer can run a full suite of on-line design simulations, and then order the fully assembled and tested customized reference design (see details on page 14). using the MOSFET. IRF9910PBF dual SO-8 The 600kHz switching frequency allows the selection of reduced size power components. All the essential components that contribute to a low cost compact solution are enclosed by the rectangular box shown on the PCB, showing a total solution size of 0.75" x 0.625" (0.7"sq). The electrical connection diagram is shown in figure 1 and the corresponding circuit schematic is shown in figure 2. +12V External Vc bias. (Optional) (J5) +3.3Vout (J4) +3.3V Vout RTN (J3) +12V RTN (J2) +12V External Vc bias RTN (J6) +12V (J1) Figure 1: IRPP3624-05A Electrical Connection Diagram Input/Output Connections J1: J2: J3: J4: J5: Input power connection terminal Input power return preferred connection terminal Output power return preferred connection terminal Output power connection terminal External bias power connection terminal. This terminal is unused for standard reference design configuration. External bias power return preferred connection terminal. This terminal is unused for standard reference design configuration. J6: Design Details The IRPP3624-05A reference design is optimized for an input voltage range of 10.8V to 13.2V and an output voltage of 3.3V at a maximum of 5A load current, www.irf.com RD#0611 3 Start-Up Procedure The 12V input power is connected between terminals J1 and J2 and the 3.3V, 5A output power is obtained through terminals J3 and J4. The VCC and VC pins are the low side driver and high side driver power input pins respectively. The VCC pin also includes the housekeeping power of the PWM controller. An under-voltage lockout (UVLO) feature is associated with each of these pins, which is set to 4.2V for VCC and 3.2V for VC. A charge pump circuit comprised of C11, D1, and C12 applies adequate voltage to the VC pin to allow fast driving capability, hence reducing the switching losses of the control FET (Q1, inside the dual-SO8 package). A 25 resistor (R11 in parallel with R12) is added in series with the charge pump circuit to maintain the VC voltage below 20V to reduce the temperature of the PWM controller IC. Upon application of the input power, the output starts ramping up to regulation within 4ms. The ramping time can be adjusted through the soft start capacitor C5. The output voltage of the synchronous buck regulator is set to 3.3V using the internal 0.6V reference voltage. The following equations are used to calculate the MOSFET power loss. Refer to the IRF9910PBF datasheet to select the parametric values of the power loss equations terms. Control FET Losses: Eq (1): PQ1 = I Q1rms 2 .RDQ1.RDn + ( I o . Qsw1 .Vin + QgQ1.Vdd + QossQ1 .Vin ).FSW I g1 Eq (3): Ptd = VSD .I o .t d .Fsw Total FET losses: Eq (4): PFET _ total = PQ1 + PQ 2 + Ptd Where, IQ1rms and IQ2rms are the rms currents for control and sync FETs respectively, in Amps IO is the output load current in Amps RD is the RDSON in ohms of the FETs and RDn is the normalized RDSON factor vs temperature extracted from the IRF9910PBF datasheet. QSW is the FET switch charge in nC VIN is the input voltage of the sync buck converter Qg is the total gate charge in nC. Vdd is the FET drive voltage, which is 8V. Ig is the drive current which is 0.5A. QOSS is the FET output charge in nC. Qrr is the sync FET internal body diode reverse recovery charge in nC VSD is the sync FET internal body diode forward voltage drop in volts. FSW is the switching frequency of the sync buck converter in hertz. td is the dead time caused by the PWM controller IC in seconds. This parameter is specified in IR3624MPBF datasheet. For design calculations related to programming the output voltage and the soft start time, selection of input/output capacitors and output inductor and control loop compensation, refer to the guidelines outlined in the IR3624MPBF PWM controller datasheet. IR's online design tool POWIR+ should be used to customize a design for applications outside the standard 10.8V to 13.2V input range and 3.3V output, and for varied design goal objectives. Synchronous FET Losses: Eq (2): QossQ2 PQ2 = I Q 2 rms2 .RDQ2 .RDn + .Vin + QgQ2 .Vdd + QrrQ2 .Vin .FSW 2 Deadtime losses: www.irf.com RD#0611 4 Layout Considerations The IRPP3624-05A reference design PCB layout offers compact design with minimum parasitics at 600kHz switching frequency. The board is designed with 4 layers using 1 oz copper weight per layer. Figures 3a through 3d represent the layout of each layer. To minimize the parasitics, the following was observed: 1. The switch node connection path is made as short as possible by placing the output inductor L1 close to the drain of the synchronous FET inside the dual SO8 package. 2. The input decoupling 10uF ceramic capacitors C1 and C2, are placed across the drain of the control FET and the ground pin of the dual SO8 package. 3. A solid ground plane is furnished in mid-layer 2. The connection of the signal ground to power ground is done at a single point in the bottom layer as shown in figure 3d. 4. The feedback track from the output VOUT to FB pin of the IC is routed as far away from noise generating traces as possible in mid-layer 2 as shown in figure 3c. www.irf.com RD#0611 5 Figure 2: Schematic Diagram for IRPP3624-05A Reference Design www.irf.com RD#0611 6 QTY 1 1 1 4 1 2 2 1 1 3 3 4 2 6 1 1 1 1 1 1 1 1 1 1 2 1 1 1 7 REF DESIGNATOR C6 C8 C7 C5, C10, C11, C12 C4 C14, C15 C1, C2 C13 D1 J1, J4, J5 J2, J3, J6 J1, J4, J5, J6 J2, J3 J1, J2, J3, J4, J5, J6 L1 R8 R9 R13 R5 R6 R4 R1 R3 R2 R11,R12 R16 Q1 U1 C3,C9, R7, R10, R14, R15 DESCRIPTION Capacitor, ceramic, 47pF, 50V,NPO, 5% Capacitor, ceramic, 3.9nF, 50V,X7R, 10% Capacitor, ceramic, 4.7nF,50V,X7R,10% Capacitor, ceramic, 0.1F, 50V, X7R, 10% Capacitor, ceramic, 1.0F, 16V, X5R, 10% Capacitor, ceramic, 10uF, 6.3V, X5R, 20% Capacitor, ceramic, 10uF, 16V, X5R, 20% Capacitor, POSCAP, 470uF, 6.3V 20% Schottky Diode, 30V,200mA Red Banana Jacks-Insulated Solder Terminal Black Banana Jacks-Insulated Solder Terminal Pan Head Slotted,screw 1/2" Pan Head Slotted,screw 1/4" Machine Screw Hex Nuts 2.2uH,8A,20m Resistor,thick film, 0 Resistor,thick film, 0 Resistor,thick film,0 Resistor,thick film,1, 5% Resistor,thick film,20, 1% Resistor,thick film,887, 1% Resistor,thick film,10k, 1% Resistor,thick film,1.5k, 1% Resistor,thick film,6.81k, 1% Resistor,thick film,49.9, 1% Resistor,thick film,6.19k, 1% Dual N FET,20V,Q1=13.4m,11nC,Q2=9. 3m,23nC PWM Controller Not installed SIZE 0603 0603 0603 0603 0603 1206 1206 7343 SOT23 4.44mm 4.44mm 7.2mmx7 mmx3mm 0805 0603 1206 0805 0603 0603 0603 0603 0603 1206 0603 SO-8 SO-8 MFR KOA KOA Phycomp TDK TDK TDK TDK SANYO IRF Johnson Johnson McMasterCarr McMasterCarr McMasterCarr DELTA ROHM ROHM KOA ROHM KOA KOA KOA KOA KOA KOA KOA IR IR PART NUMBER NPO0603HTTD470J 0603X7RHT392K 06032R472K8B20 C1608X7R1H104K C1608X5R1C105K C3216X5R0J106M C3216X5R1C106M 6TPB470M BAT54S 108-0902-001 108-0903-001 91792A081 91792A077 91841A003 MPO73-2R2IR MCR10EZHJ000 MCR03EZHJ000 RM73Z2B000 MCR10EZHJ1R0 RK73H1JLTD20R0F RK73H1J8870F RK73H1J1002F RK73H1J1501F RK73H1JLTD6811F RK73H2B49R9F RK73H1JLTD6191F IRF9910PBF IR3624MPBF Table 1 - Complete Bill of Materials for IRPP3624-05AReference Design www.irf.com RD#0611 7 Figure 3a: IRPP3624-05A Reference Design top layer placement and layout. Figure 3b: IRPP3624-05A Reference Design mid-layer1 ground plane www.irf.com RD#0611 8 Figure 3c: IRPP3624-05A Reference Design mid-layer2 layout. Figure 3d: IRPP3624-05A Reference Design bottom layer layout. www.irf.com RD#0611 9 IRPP3624-05A Efficiency 89% 88% 87% 86% 85% Efficiency 84% 83% 82% 81% 80% 79% 78% 77% 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 Load Current (Amps) Figure 4a: IRPP3624-05A Reference Design Electrical Efficiency IRPP3624-05A System Power Loss 12Vin, 3.3Vout, 250C, 0LFM 2.25 2.00 Power Loss (Watts) 1.75 1.50 1.25 1.00 0.75 1 2 2 3 3 4 4 5 5 Load Current (Amps) Figure 4b: IRPP3624-05A Reference Design Power Loss Curve www.irf.com RD#0611 10 Vin=12V,Vout=3.3V,Io Q1 IC Max 72.8 Max 71.9 L1 Max 64.7 Figure 5: IRPP3624-05A Reference Design Thermograph at 5A load Phase Plot Gain Plot Phmargin= 72 F0=67kHz Figure 6: IRPP3624-05A Reference Design Bode Plot of the Control Loop at 5A load. www.irf.com RD#0611 11 Figure 7: Input ripple, IO=5A Figure 8: Output ripple, IO=5A www.irf.com RD#0611 12 Figure 9: Output Voltage transients, load: 1A to 5A to 1A, di/dt=2.5A/us Figure 10: Hiccup mode, response to output short circuit www.irf.com RD#0611 13 Figure 11: Power up. Ch1=VIN, Ch2=VOUT, Ch3=Soft Start Figure 12: Power down. Ch1=VIN, Ch2=VOUT, Ch3=Soft Start www.irf.com RD#0611 14 Part Number IRPP3624-05A Input Voltage 12V Output Voltage 3.3V Output Current 5A Switching Frequency 600kHz Power Semi BOM IR3624MPBF (MLPD-3x3) IRF8910PBF (Dual SO-8) IR3624MPBF (MLPD-3x3) IRF7823PBF (SO-8) IRF7832ZPBF (SO-8) Delivery Time Comments Standard Reference Design Fixed BOM 24 - 48 hrs IRPP3624-12A 12V 1.8V 12A 600kHz Table 2 - Complete IRPP3624-xxA Reference Design Selector Table www.irf.com RD#0611 15 |
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